Gate array

Results: 1402



#Item
201Computing:91–102 DOIs00607Aligning the representation and reality of computation with asynchronous logic automata Neil Gershenfeld

Computing:91–102 DOIs00607Aligning the representation and reality of computation with asynchronous logic automata Neil Gershenfeld

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Source URL: www.cba.mit.edu

Language: English - Date: 2011-12-17 09:30:36
202Sub-Nanoseconds Time Measurement Systems: USB2.0-TDC Series Device Dual Channel USB2.0-TDC No. of GPX Chips

Sub-Nanoseconds Time Measurement Systems: USB2.0-TDC Series Device Dual Channel USB2.0-TDC No. of GPX Chips

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Source URL: surface-concept.com

Language: English - Date: 2010-05-07 07:43:17
203Overview of *configurable* architectures Prof. Kurt Keutzer EECS  Thanks to Andre Dehon, Jan Rabaey, and many vendors

Overview of *configurable* architectures Prof. Kurt Keutzer EECS Thanks to Andre Dehon, Jan Rabaey, and many vendors

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Source URL: www.cs.berkeley.edu

Language: English
204AEGISOLVE, INC. 415 Fairchild Dr. Mountain View, CaliforniaUSA Tel: Fax: Notice pursuant to Sectionof the Testing Authorization and Test Suite Licensing

AEGISOLVE, INC. 415 Fairchild Dr. Mountain View, CaliforniaUSA Tel: Fax: Notice pursuant to Sectionof the Testing Authorization and Test Suite Licensing

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Source URL: dcimovies.com

Language: English - Date: 2014-11-23 21:18:00
205AEGISOLVE, INC. 415 Fairchild Dr. Mountain View, CaliforniaUSA Tel: Fax: Notice pursuant to Sectionof the Testing Authorization and Test Suite Licensing

AEGISOLVE, INC. 415 Fairchild Dr. Mountain View, CaliforniaUSA Tel: Fax: Notice pursuant to Sectionof the Testing Authorization and Test Suite Licensing

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Source URL: dcimovies.com

Language: English - Date: 2014-12-02 18:30:59
206Small, Stupid, and Scalable: Secure Computing with Faerieplay∗ Alexander Iliev Sean W. Smith

Small, Stupid, and Scalable: Secure Computing with Faerieplay∗ Alexander Iliev Sean W. Smith

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Source URL: www.cs.dartmouth.edu

Language: English - Date: 2010-11-08 12:53:14
207Fast Onboard Stereo Vision for UAVs Andrew J. Barry1 , Helen Oleynikova2 , Dominik Honegger2 , Marc Pollefeys2 , and Russ Tedrake1 I. I NTRODUCTION In the last decade researchers have built incredible new capabilities fo

Fast Onboard Stereo Vision for UAVs Andrew J. Barry1 , Helen Oleynikova2 , Dominik Honegger2 , Marc Pollefeys2 , and Russ Tedrake1 I. I NTRODUCTION In the last decade researchers have built incredible new capabilities fo

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Source URL: abarry.org

Language: English - Date: 2015-04-12 15:14:08
208Microsoft Word - Hardware Schematic Description.docx

Microsoft Word - Hardware Schematic Description.docx

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Source URL: www.goes-r.gov.

Language: English - Date: 2015-04-21 17:17:10
209L1 FPD – Trigger Implementation for DFE  1 Introduction L1 FPD equations implementation 1 has been conceived in order to use the three devices, FPGA 2, located into the DFE Double Wide Daughter Board (DWDB). Each devic

L1 FPD – Trigger Implementation for DFE 1 Introduction L1 FPD equations implementation 1 has been conceived in order to use the three devices, FPGA 2, located into the DFE Double Wide Daughter Board (DWDB). Each devic

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Source URL: d0server1.fnal.gov

Language: English - Date: 2002-07-31 23:32:43
210www.xjtag.com  XJAnalyser Overview

www.xjtag.com XJAnalyser Overview

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Source URL: www.etoolsmiths.com

Language: English - Date: 2014-01-08 03:14:22